1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a low resistance poly-Si/metal gate structure for MOS applications.
2) Description of the Prior Art
As MOS dimensions are reduced, the contact resistance and sheet resistance increase. In conventional gate electrodes using polysilicon/silicide, such as Poly-Si/WSi.sub.x, the increased resistance causes a large gate RC delay, thereby degrading performance. This is particularly detrimental in high speed memory chip and logic device applications.
One approach to overcoming the problems caused by high gate resistance in Poly-Si/silicide gate electrodes is disclosed by Sitaram (5,384,285). Resistance in a Poly-Si/Silicide gate electrode can be reduced by preventing detrimental transition-metal reactions during processing, particularly with oxygen. Sitaram prevents reactions with the transition-metal layer by forming a boron nitride or boron oxynitride capping layer over the transition metal layer. The capping layer is removed after formation of the silicide. While this approach lowers the sheet resistance of the silicide layer, it does not achieve the low contact resistance or overall gate electrode resistance of the composite poly-Si/tungsten gate electrode of the present invention. Nor does it provide the thermal stability of the present invention.
Similarly, Apte et al. (5,593,924) disclose the use of a removable capping layer composed of a metal such as titanium nitride to reduce contamination in a silicide layer; thereby lowering sheet resistance. Again, this invention does not address the other problems associated with Poly-Si/silicide gate electrodes described previously.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,384,285 (Sitaram et al.) and U.S. Pat. No. 5,593,924 (Apte) described above, as well as, the following US Patents.
U.S. Pat. No. 5,103,272 (Nishiyama) shows a process for forming titanium silicide contacts on a polysilicon gate and source and drain regions using a titanium nitride barrier layer to prevent the titanium silicide layer from agglomerating.
U.S. Pat. No. 5,550,079 (Lin) shows a silicide shunt with a tungsten nitride barrier layer.
U.S. Pat. No. 5,668,065 (Lin) shows a polysilicon/tungsten silicide/silicon nitride gate structure.